상 변환 메모리 수명 향상을 위한 캐시 라인 교체 정책

Abstract

Phase Change Memory (PCM) is one of the most promising technologies for non-volatile random access memory architectures. Implementing a main memory using PCM provides many benefits such as high density, non-volatility, bit alterability, random access and no refresh requirement. However, using PCM as a main memory technology is only possible if the write endurance problem is first solved effectively. With a PCM device, there is a limit on the number of times each bit cell can be written-typically on the order of about 107 writes per bit cell. This thesis presents a new cache line replacement policy that is claimed to be an effective mixed policy that is formed by assigning weights to each of several possible cache line replacement policies, By using an appropriate set of weights, It is possible to either increase the cache hit ratio or decrease the number of write to “hot” memory addresses, thereby resulting in a significant extension of the expected PCM lifetimes, at the expense of a slight reduction in cache hit rates. Simulation results show that the proposed policy results in up to 60% improvement in PCM expected lifetime over previously proposed methods.