Saturation of threshold-voltage shift during positive bias temperature instability in HfSiON/SiO2 n-channel MOSFET and its effect on device lifetime evaluation

Abstract

This paper investigates the saturation of threshold-voltage shift Delta V-th of HfSiON/SiO2 n-channel MOSFETs (nMOFSETs) under positive bias temperature instability (PBTI) and proposes an empirical PBTI degradation model that can predict operational lifetime t(L) accurately. Experimental results indicate that secondary-hole trapping occurred in the bulk dielectric due to hole injection at the anode after electron trapping in the initial bulk trap. This secondary-hole trapping causes a decrease in the time exponent n of the power law Delta V-th proportional to t(n) in as the gate stress voltage V-g,V-str increases. This dependency of n on Vg,str results in overestimation of t(L) when it was estimated using the conventional method which assumes a constant value of n. An empirical model that considers the effect of V-g,V-str on n is proposed; this model predicted operational t(L) = 2.6 x 10(5)s, which agreed well with experimentally-measured t(L) = 3.9 x 10(5)s. (C) 2014 The Japan Society of Applied Physics