SRAM Write-Ability Improvement with Transient Negative Bit-Line Voltage
SCIE
SCOPUS
- Title
- SRAM Write-Ability Improvement with Transient Negative Bit-Line Voltage
- Authors
- SRAM Write-Ability Improvement with Transient Negative Bit-L; Rahul Rao; Kim, JJ; Ching-Te Chuang
- Date Issued
- 2011-01
- Publisher
- IEEE
- Abstract
- Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10(3) X reduction in the Write-failure probability with the proposed method.
- Keywords
- Capacitive coupling; SRAM; variation; write-ability; ENHANCEMENT; SCHEME; DESIGN; CMOS
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/14740
- DOI
- 10.1109/TVLSI.2009.2029114
- ISSN
- 1063-8210
- Article Type
- Article
- Citation
- IEEE Trans. on VLSI Systems, vol. 19, no. 1, page. 24 - 32, 2011-01
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