DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ik-Joon Chang | - |
dc.contributor.author | Kim, JJ | - |
dc.contributor.author | Keejong Kim | - |
dc.contributor.author | Kaushik Roy | - |
dc.date.accessioned | 2016-03-31T08:10:57Z | - |
dc.date.available | 2016-03-31T08:10:57Z | - |
dc.date.created | 2014-03-09 | - |
dc.date.issued | 2011-08 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.other | 2011-OAK-0000029381 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/14741 | - |
dc.description.abstract | For ultra low power application, digital sub-threshold logic design has been explored. Extremely low power supply (VDD) of sub-threshold logic results in significant power reduction. However, it is difficult to convert signals from core logic to input/output (I/O) circuits since core VDD is vastly different from high I/O supply voltage. In this work, we propose a level converter based on dynamic logic style for sub-threshold I/O part, having a large dynamic range of conversion. For the level converter, high voltage clock signal needs to be delivered through separate clock path from core logic, leading to clock synchronization problem between high voltage and low voltage clocks. To overcome this issue, we employed a Clock Synchronizer. A test chip is fabricated in 130-nm CMOS technology in order to verify the proposed technique. Hardware measurement results show that the level converter successfully converts 0.3 V 8 MHz pulse to 2.5 V signal. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE Trans. on VLSI Systems | - |
dc.subject | Level converter | - |
dc.subject | subthreshold logic | - |
dc.subject | subthreshold operation | - |
dc.subject | ultra-low voltage operation | - |
dc.subject | VOLTAGE | - |
dc.subject | DESIGN | - |
dc.title | Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V | - |
dc.type | Article | - |
dc.contributor.college | 창의IT융합공학과 | - |
dc.identifier.doi | 10.1109/TVLSI.2010.2051240 | - |
dc.author.google | Chang, IJ | - |
dc.author.google | Kim, JJ | - |
dc.author.google | Kim, K | - |
dc.author.google | Roy, K | - |
dc.relation.volume | 19 | - |
dc.relation.issue | 8 | - |
dc.relation.startpage | 1429 | - |
dc.relation.lastpage | 1437 | - |
dc.contributor.id | 11244586 | - |
dc.relation.journal | IEEE Trans. on VLSI Systems | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE Trans. on VLSI Systems, v.19, no.8, pp.1429 - 1437 | - |
dc.identifier.wosid | 000293712100010 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 1437 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1429 | - |
dc.citation.title | IEEE Trans. on VLSI Systems | - |
dc.citation.volume | 19 | - |
dc.contributor.affiliatedAuthor | Kim, JJ | - |
dc.identifier.scopusid | 2-s2.0-79960994384 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 16 | - |
dc.description.scptc | 21 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Level converter | - |
dc.subject.keywordAuthor | subthreshold logic | - |
dc.subject.keywordAuthor | subthreshold operation | - |
dc.subject.keywordAuthor | ultra-low voltage operation | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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