Characterization and Modeling of 1/f Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

Abstract

In this paper, the volume trap densities N(t) are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting N(t), the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/f model developed is discussed.