DC Field | Value | Language |
---|---|---|
dc.contributor.author | Dongki Kim | - |
dc.contributor.author | YOO, SUNGJOO | - |
dc.contributor.author | Lee, SG | - |
dc.date.accessioned | 2016-03-31T08:11:16Z | - |
dc.date.available | 2016-03-31T08:11:16Z | - |
dc.date.created | 2014-03-06 | - |
dc.date.issued | 2013-06 | - |
dc.identifier.issn | 1539-9087 | - |
dc.identifier.other | 2013-OAK-0000029368 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/14753 | - |
dc.description.abstract | The network-on-chip (NoC) plays a crucial role in memory performance due to the fact that it can handle the majority of traffics from/to the DRAM memory controllers. However, there has been little work on the interplay between the NoC and memory controllers. In this article, we address a problem called network congestion-induced memory blocking and propose a novel memory controller, which performs memory access scheduling and network entry control in a network congestion-aware manner. In case of network congestion, in order to avoid performance degradation due to the blocking caused by data bound for congested regions in the NoC, the proposed memory controller favors requests and data associated with uncongested regions. In addition, in order to avoid the fairness problem of such a policy, we also propose a gradual method, which enables a trade-off between performance (in memory utilization) and fairness (in memory access latency). Experimental results show that the proposed method can offer up to 1.76 similar to 2.99 times improvement in memory utilization in the latency-tolerant designs. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | ACM | - |
dc.relation.isPartOf | ACM Transactions on Embedded Systems (TECS) | - |
dc.title | A Network Congestion-Aware Memory Subsystem for Manycore | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1145/2485984.2485998 | - |
dc.author.google | Kim, DK | - |
dc.author.google | Yoo, SJ | - |
dc.author.google | Lee, SG | - |
dc.relation.volume | 12 | - |
dc.relation.issue | 4 | - |
dc.contributor.id | 10204448 | - |
dc.relation.journal | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | ACM Transactions on Embedded Systems (TECS), v.12, no.4 | - |
dc.identifier.wosid | 000321217900013 | - |
dc.date.tcdate | 2018-03-23 | - |
dc.citation.number | 4 | - |
dc.citation.title | ACM Transactions on Embedded Systems (TECS) | - |
dc.citation.volume | 12 | - |
dc.contributor.affiliatedAuthor | YOO, SUNGJOO | - |
dc.contributor.affiliatedAuthor | Lee, SG | - |
dc.identifier.scopusid | 2-s2.0-84881309373 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.scptc | 1 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Design | - |
dc.subject.keywordAuthor | Performance | - |
dc.subject.keywordAuthor | DRAM | - |
dc.subject.keywordAuthor | memory access scheduling | - |
dc.subject.keywordAuthor | network-on-chip | - |
dc.subject.keywordAuthor | memory blocking | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
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