An 8GB/s Quad-Skew Cancelling Parallel Transceiver for High-Speed DRAM Interface

Abstract

This paper presents the first quad-deskewing 8GB/s transceiver for Quad-based memory interface with individual data edge tracking CDRs used both in TX and RX. In chip-to-chip interfaces with multiphase clocks, impact of quad-skew steadily increases, in company with data rate. We adopted digital quad-skew detector because analog circuit is sensitive to mismatch. For the first time the mismatch of the 4-to-1 serializer is corrected by the proposed individual data edge tracking CDR used in the TX. The proposed CDR utilizes individual phase control to correct skew in the edge clocks and multiphase generation to cancel skew in the data clocks. The quad-skew cancelling in the TX reduces quad-skew ~ 5ps. The proposed quad-skew cancelling is an improvement on the existing quad-skew cancelling, and the proposed transceiver provides suitable architecture for high-speed QDR-based DRAM interface. The transmitter, implemented in a 90nm CMOS, shows 8 Gb/s/channel with a BER of 10 -12 and a power consumption of 4.02mW/Gb/s.