공정산포 자체 보정 기능을 갖는 Spike-Based VLSI Winner-Take-All Network

Abstract

This paper presents a neuromorphic IC based-on winner-take-all (WTA) network. To reduce the effect of the process variations on synaptic weight, a digitally controlled self-calibration scheme is proposed. For spike-based multi-chip interface, Pseudo Address-Event-Representation (AER) is presented. The WTA network is designed with 64 neurons and 4000 synapses using 65nm-CMOS technology, showing successful soft and hard WTA functions by compensating mismatches among the synapses. The proposed WTA network shows improvement in eliminating weight mismatch and has the potential to be used for recognition and decision process of neural network system.