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Cited 10 time in webofscience Cited 11 time in scopus
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dc.contributor.authorHwang, EJ-
dc.contributor.authorKim, W-
dc.contributor.authorKim, YH-
dc.date.accessioned2016-03-31T08:24:07Z-
dc.date.available2016-03-31T08:24:07Z-
dc.date.created2013-12-17-
dc.date.issued2013-10-
dc.identifier.issn1063-8210-
dc.identifier.other2013-OAK-0000028411-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/15222-
dc.description.abstractThis paper focuses on statistical optimization and, more specifically, timing yield (TY)-constrained optimization. For cell replacement in timing-constrained optimization, we need an indicator that examines whether or not a timing violation occurs and gives the available timing for a gate. In deterministic optimization, the timing slack is used for this indicator. Although there is an analogous concept of TY slack in statistical optimization, it has not been well utilized. This paper proposes an effective way to use the TY slack for successful statistical optimization. To achieve this, we present an efficient method to calculate the TY slacks of gates and a strategy that uses timing resources for effective statistical optimization. Based on this work, we propose a novel statistical leakage minimization method that uses the TY slack for a gate change metric. The use of TY-based metrics that are appropriate for statistical design ensures that our method has a better optimization performance at a higher speed. Experimental results on ISCAS-85 benchmark circuits show that the leakage minimization method reduces leakage by 25.2% compared to the statistical benchmark method. In addition, our method has a better runtime when the number of gates is high.-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherIEEE Circuits and Systems Society-
dc.relation.isPartOfIEEE Transactions on Very Large Scale Integration Systems-
dc.subjectProcess variation-
dc.subjectstatistical design-
dc.subjectstatistical leakage minimization-
dc.subjectstatistical optimization-
dc.subjectstatistical static timing analysis (SSTA)-
dc.subjecttiming yield-constrained optimization-
dc.subjecttiming yield slack-
dc.subjectFULL-CHIP LEAKAGE-
dc.subjectSPATIAL CORRELATIONS-
dc.subjectTHRESHOLD VOLTAGE-
dc.subjectPOWER-
dc.subjectVARIABILITY-
dc.subjectPERFORMANCE-
dc.subjectCIRCUITS-
dc.subjectTECHNOLOGY-
dc.subjectACCURATE-
dc.titleTiming Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization-
dc.typeArticle-
dc.contributor.college전자전기공학과-
dc.identifier.doi10.1109/TVLSI.2012.2220792-
dc.author.googleHwang, EJ-
dc.author.googleKim, W-
dc.author.googleKim, YH-
dc.relation.volume21-
dc.relation.issue10-
dc.relation.startpage1783-
dc.relation.lastpage1796-
dc.contributor.id10176127-
dc.relation.journalIEEE Transactions on Very Large Scale Integration Systems-
dc.relation.indexSCI급, SCOPUS 등재논문-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE Transactions on Very Large Scale Integration Systems, v.21, no.10, pp.1783 - 1796-
dc.identifier.wosid000324650300002-
dc.date.tcdate2019-01-01-
dc.citation.endPage1796-
dc.citation.number10-
dc.citation.startPage1783-
dc.citation.titleIEEE Transactions on Very Large Scale Integration Systems-
dc.citation.volume21-
dc.contributor.affiliatedAuthorKim, YH-
dc.identifier.scopusid2-s2.0-84884590007-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc6-
dc.description.scptc7*
dc.date.scptcdate2018-05-121*
dc.type.docTypeArticle-
dc.subject.keywordPlusFULL-CHIP LEAKAGE-
dc.subject.keywordPlusPOWER-
dc.subject.keywordPlusVARIABILITY-
dc.subject.keywordPlusCIRCUITS-
dc.subject.keywordPlusACCURATE-
dc.subject.keywordPlusVOLTAGE-
dc.subject.keywordAuthorProcess variation-
dc.subject.keywordAuthorstatistical design-
dc.subject.keywordAuthorstatistical leakage minimization-
dc.subject.keywordAuthorstatistical optimization-
dc.subject.keywordAuthorstatistical static timing analysis (SSTA)-
dc.subject.keywordAuthortiming yield-constrained optimization-
dc.subject.keywordAuthortiming yield slack-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-

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김영환KIM, YOUNG HWAN
Dept of Electrical Enginrg
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