A 1.25 ps Resolution 8b Cyclic TDC in 0.13 mu m CMOS

Abstract

This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2x time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 mu m CMOS, shows a resolution of 1.25 ps with a total conversion range of +/-160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are +/-0.7 LSB and -3 to +1 LSB, respectively.