DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jee, DW | - |
dc.contributor.author | Kim, B | - |
dc.contributor.author | Park, HJ | - |
dc.contributor.author | Sim, JY | - |
dc.date.accessioned | 2016-03-31T08:43:25Z | - |
dc.date.available | 2016-03-31T08:43:25Z | - |
dc.date.created | 2013-03-05 | - |
dc.date.issued | 2012-11 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.other | 2012-OAK-0000026857 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/15906 | - |
dc.description.abstract | This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent Delta Sigma time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent Delta Sigma TDC generates adaptively scaled exponent-only information to track the finest resolution that prevents overloading for a given input environment. In addition, IIR-based noise cancellation provides easy filtering of delta-sigma modulator noise without tightened matching constraints. The DPLL fabricated in 0.13-mu m CMOS consumes 8.6 mW and shows the subexponent operation and IIR noise cancellation. The measured phase noise of DPLL is -98 dBc/Hz at 200-kHz offset and -111 dBc/Hz at 3-MHz offset with 500-kHz loop bandwidth. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.subject | Delta-sigma time-to-digital converter (TDC) | - |
dc.subject | digital phase-locked loop (DPLL) | - |
dc.subject | fractional-N phase-locked loop (PLL) | - |
dc.subject | noise cancellation | - |
dc.subject | subexponent TDC | - |
dc.subject | CONVERTER | - |
dc.subject | TIME | - |
dc.title | A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation | - |
dc.type | Article | - |
dc.contributor.college | 정보전자융합공학부 | - |
dc.identifier.doi | 10.1109/TCSII.2012.2228373 | - |
dc.author.google | Jee, DW | - |
dc.author.google | Kim, B | - |
dc.author.google | Park, HJ | - |
dc.author.google | Sim, JY | - |
dc.relation.volume | 59 | - |
dc.relation.issue | 11 | - |
dc.relation.startpage | 721 | - |
dc.relation.lastpage | 725 | - |
dc.contributor.id | 10071836 | - |
dc.relation.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.59, no.11, pp.721 - 725 | - |
dc.identifier.wosid | 000313426100005 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 725 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 721 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 59 | - |
dc.contributor.affiliatedAuthor | Kim, B | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.identifier.scopusid | 2-s2.0-84872106128 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 2 | - |
dc.description.scptc | 2 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Delta-sigma time-to-digital converter (TDC) | - |
dc.subject.keywordAuthor | digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | fractional-N phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | noise cancellation | - |
dc.subject.keywordAuthor | subexponent TDC | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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