A 650Mb/s-to-8Gb/s Referenceless CDR with Automatic Acquisition of Data Rate and a 1.25 ps Resolution Sub-Exponent TDC for All-Digital PLL

Abstract

In this thesis, a 650Mb/s-to-8Gb/s locking referenceless CDR circuit with automatic frequency acquisition and 1.25ps resolution sub-exponent TDC are proposed with an all-digital PLL with the TDC as a design example.Firstly, a 650Mb/s-to-8Gb/s referenceless CDR circuit is proposed with an automatic tracking of data-rate. For efficient frequency acquisition, a DLL-based loop is used with a simple phase/frequency detector. The CDR, implemented in a 65nm CMOS, shows a BER of less than 10-12 with the best performance in lock-range, power consumption, and size compared with previously reported continuous-rate CDRs.Secondly, an all-digital PLL for clock generation of wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2x time amplifiers, the TDC efficiently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time amplifier. The TDC, implemented in a 0.18 m CMOS, shows the minimum resolution of 1.25 ps with a total conversion range of 2.5ns, the maximum operating frequency of 250MHz, and power consumption of 1.8mW at 60MHz. The measured rms jitter of PLL was 5.03 ps at 960 MHz.