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New Insight Into PBTI Evaluation Method for nMOSFETs With Stacked High-k/IL Gate Dielectric SCIE SCOPUS

Title
New Insight Into PBTI Evaluation Method for nMOSFETs With Stacked High-k/IL Gate Dielectric
Authors
Lee, SKJo, MSohn, CWKang, CYLee, JCJeong, YHLee, BH
Date Issued
2012-11
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
In this letter, a strategy to minimize the error in lifetime projections using a positive bias temperature instability (PBTI) test has been proposed. Two distinctly different projection slopes were observed in a plot of time to failure versus oxide electric field. A small slope in the high-field region, which means weaker electric field dependence, led to an underestimation of lifetime. This result was attributed to a filled trap cluster at a specific trap energy level, locally reducing the oxide electric field. Thus, different lifetimes can be projected depending on stress bias. Maintaining a PBTI stress bias range below this trap energy level is recommended for accurate projections.
Keywords
HfO2; lifetime; nMOSFET; positive bias temperature instability (PBTI); trap cluster
URI
https://oasis.postech.ac.kr/handle/2014.oak/16268
DOI
10.1109/LED.2012.2211072
ISSN
0741-3106
Article Type
Article
Citation
IEEE ELECTRON DEVICE LETTERS, vol. 33, no. 11, page. 1517 - 1519, 2012-11
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정윤하JEONG, YOON HA
Dept of Electrical Enginrg
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