DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, NH | - |
dc.contributor.author | Kim, H | - |
dc.contributor.author | Kang, B | - |
dc.date.accessioned | 2016-03-31T09:10:14Z | - |
dc.date.available | 2016-03-31T09:10:14Z | - |
dc.date.created | 2012-03-19 | - |
dc.date.issued | 2012-02 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.other | 2012-OAK-0000024938 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/16755 | - |
dc.description.abstract | This letter investigates the impact of dynamic stress on the degradation of a nanoscale p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET). Experimental results indicate that the OFF-state stress generated donorlike interface traps N-it and electron oxide traps, localized near the drain. The ON-state stress produced the negative bias temperature instability which generated N-it's and positive oxide charges Q(ox) distributed uniformly in the channel. Although the electrons trapped by the OFF-state stress decreased the threshold voltage vertical bar V-th vertical bar, they were detrapped readily by the subsequent ON-state stress. A dynamic stress caused the nanoscale pMOSFET to build up N-it and positive Q(ox), which increased the vertical bar V-th vertical bar significantly. These new observations indicate that the combined dynamic process can significantly influence the reliability of scaled CMOS inverter circuits. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGI | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.subject | Interface trap | - |
dc.subject | MOSFET | - |
dc.subject | negative bias temperature instability (NBTI) | - |
dc.subject | OFF-state stress | - |
dc.subject | oxide charge | - |
dc.subject | NBTI | - |
dc.subject | GENERATION | - |
dc.subject | MOSFETS | - |
dc.subject | VOLTAGE | - |
dc.title | Impact of Off-State Stress and Negative Bias Temperature Instability on Degradation of Nanoscale pMOSFET | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1109/LED.2011.2174026 | - |
dc.author.google | Lee, NH | - |
dc.author.google | Kim, H | - |
dc.author.google | Kang, B | - |
dc.relation.volume | 33 | - |
dc.relation.issue | 2 | - |
dc.relation.startpage | 137 | - |
dc.relation.lastpage | 139 | - |
dc.contributor.id | 10071834 | - |
dc.relation.journal | IEEE ELECTRON DEVICE LETTERS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.33, no.2, pp.137 - 139 | - |
dc.identifier.wosid | 000299812300003 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 139 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 137 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 33 | - |
dc.contributor.affiliatedAuthor | Kang, B | - |
dc.identifier.scopusid | 2-s2.0-84856259027 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 9 | - |
dc.description.scptc | 8 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | NBTI | - |
dc.subject.keywordPlus | GENERATION | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordAuthor | Interface trap | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | negative bias temperature instability (NBTI) | - |
dc.subject.keywordAuthor | OFF-state stress | - |
dc.subject.keywordAuthor | oxide charge | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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