A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-mu m CMOS
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- Title
- A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-mu m CMOS
- Authors
- Young-Hun Seo; Seon-Kyoo Lee; SIM, JAE YOON
- Date Issued
- 2011-02
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- A new concept of floating-point-number representation is implemented in a time-to-digital converter (TDC), which adaptively scales its resolution according to the amount of input difference. With a fixed 6-bit significand number, the TDC provides five cases of the exponent (x1, x2, x4, x8, and x16) to indicate the scale information. A digital phase-locked loop (PLL) with the TDC is implemented in a 0.18-mu m CMOS. The TDC shows the minimum resolution of 3 ps with a total conversion range of 3.5 ns, the maximum operating frequency of 80 MHz, and the power consumption of 18 mW at 75 MHz. The PLL shows a lock range of 0.9-1.25 GHz and a root-mean-square jitter of 3.5 ps at 1.2 GHz.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/17575
- DOI
- 10.1109/TCSII.2011.2106315
- ISSN
- 1549-7747
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 58, no. 2, page. 70 - 74, 2011-02
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