Optimum design for linearity and efficiency of a microwave Doherty amplifier using a new load matching technique

Abstract

A Doherty amplifier with full load matching circuits of the carrier and peaking amplifiers at both low and high power levels is demonstrated for the first time. In the circuit design, sections of transmission lines are inserted in the load matching, network for power-level-dependent load impedances. The circuit elements and bias points are designed and optimized using a large-signal harmonic balance simulation to offer simultaneous improvements in linearity and efficiency. Two 1.4 GHz Doherty amplifiers have been implemented using silicon LDMOS FETs. The RF performances of the Doherty amplifier-I (a combination of a class B carrier amplifier and a bias-tuned class C peaking amplifier) have been compared with those of a class B amplifier alone. The Doherty amplifier-II (a combination Of a class AB carrier amplifier and a bias-tuned class C peaking amplifier) has been compared with a class AB amplifier alone. The new Doherty amplifiers show an improved linearity as well as higher efficiency.