DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, YH | - |
dc.contributor.author | Park, J | - |
dc.contributor.author | Kim, S | - |
dc.date.accessioned | 2016-03-31T13:14:13Z | - |
dc.date.available | 2016-03-31T13:14:13Z | - |
dc.date.created | 2009-03-20 | - |
dc.date.issued | 2002-02 | - |
dc.identifier.issn | 0740-817X | - |
dc.identifier.other | 2001-OAK-0000002229 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/19374 | - |
dc.description.abstract | In semiconductor manufacturing, the key production criteria are a short cycle time and the maximization of the production capacity. It is known that the production capacity mainly depends on the bottleneck machines in the photolithography processes used in the fabrication process. In this paper we suggest a model to allow the testing of various policies without losing the main characteristics of the fabrication line. Efficient scheduling rules for the bottlenecks and input rules are also suggested with the objectives of maximizing the production volume under a short cycle time. We have shown that pull type scheduling rules outperform push type rules for most performance measures, and that there exists a good combination of scheduling and input rules. Experimental results also include the relationships among the cycle time, balance rate, production output and delivery performance. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | KLUWER ACADEMIC PUBL | - |
dc.relation.isPartOf | IIE TRANSACTIONS | - |
dc.subject | WEIGHTED TARDINESS | - |
dc.subject | WAFER FABRICATION | - |
dc.subject | CYCLE TIME | - |
dc.subject | INDUSTRY | - |
dc.subject | SYSTEM | - |
dc.subject | MODELS | - |
dc.title | Experimental study on input and bottleneck scheduling for a semiconductor fabrication line | - |
dc.type | Article | - |
dc.contributor.college | 기술경영 대학원 과정 | - |
dc.identifier.doi | 10.1080/07408170208928860 | - |
dc.author.google | Lee, YH | - |
dc.author.google | Park, J | - |
dc.author.google | Kim, S | - |
dc.relation.volume | 34 | - |
dc.relation.issue | 2 | - |
dc.relation.startpage | 179 | - |
dc.relation.lastpage | 190 | - |
dc.contributor.id | 10073810 | - |
dc.relation.journal | IIE TRANSACTIONS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IIE TRANSACTIONS, v.34, no.2, pp.179 - 190 | - |
dc.identifier.wosid | 000171291800008 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 190 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 179 | - |
dc.citation.title | IIE TRANSACTIONS | - |
dc.citation.volume | 34 | - |
dc.contributor.affiliatedAuthor | Kim, S | - |
dc.identifier.scopusid | 2-s2.0-0036468738 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 36 | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | WEIGHTED TARDINESS | - |
dc.subject.keywordPlus | WAFER FABRICATION | - |
dc.subject.keywordPlus | CYCLE TIME | - |
dc.subject.keywordPlus | INDUSTRY | - |
dc.subject.keywordPlus | SYSTEM | - |
dc.subject.keywordPlus | MODELS | - |
dc.relation.journalWebOfScienceCategory | Engineering, Industrial | - |
dc.relation.journalWebOfScienceCategory | Operations Research & Management Science | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Operations Research & Management Science | - |
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