DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeong, MY | - |
dc.contributor.author | Lee, BH | - |
dc.contributor.author | Jeong, YH | - |
dc.date.accessioned | 2016-03-31T13:15:31Z | - |
dc.date.available | 2016-03-31T13:15:31Z | - |
dc.date.created | 2009-08-05 | - |
dc.date.issued | 2001-03 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.other | 2001-OAK-0000002161 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/19423 | - |
dc.description.abstract | We have investigated design considerations for low-power single-electron transistor (SET) logic circuits. Supply-voltage scaling is introduced as a method for reducing the power consumption of SET circuits. A detailed analysis of the effects of supply-voltage scaling is given on the basis of the behavior of a complementary capacitively coupled SET inverter circuit. It has been shown that the hysteresis caused by the supply-voltage-dependent threshold voltage of a SET quickly disappears as the temperature rises, and does not ruin the desired inverting operation at a practical operation temperature. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. From the results of power-delay product and delay time. it has been shown that the supply-voltage scaling should be carried out within 20% of maximum supply-voltage to maintain overall circuit performance. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | INST PURE APPLIED PHYSICS | - |
dc.relation.isPartOf | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | - |
dc.subject | single-electron transistor | - |
dc.subject | single-electron transistor logic | - |
dc.subject | Coulomb blockade | - |
dc.subject | power consumption | - |
dc.subject | GATE | - |
dc.title | Design considerations for low-power single-electron transistor logic circuits | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1143/JJAP.40.2054 | - |
dc.author.google | Jeong, MY | - |
dc.author.google | Lee, BH | - |
dc.author.google | Jeong, YH | - |
dc.relation.volume | 40 | - |
dc.relation.issue | 3B | - |
dc.relation.startpage | 2054 | - |
dc.relation.lastpage | 2057 | - |
dc.contributor.id | 10106021 | - |
dc.relation.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Conference Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, v.40, no.3B, pp.2054 - 2057 | - |
dc.identifier.wosid | 000170771600130 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 2057 | - |
dc.citation.number | 3B | - |
dc.citation.startPage | 2054 | - |
dc.citation.title | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | - |
dc.citation.volume | 40 | - |
dc.contributor.affiliatedAuthor | Jeong, YH | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 6 | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | single-electron transistor | - |
dc.subject.keywordAuthor | single-electron transistor logic | - |
dc.subject.keywordAuthor | Coulomb blockade | - |
dc.subject.keywordAuthor | power consumption | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
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