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Two-phase back-bias generator for low-voltage gigabit DRAMs SCIE SCOPUS
- Title
- Two-phase back-bias generator for low-voltage gigabit DRAMs
- Date Issued
- 1998-09-17
- Publisher
- IEE-INST ELEC ENG
- Abstract
- A two-phase back-bias (V-BB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of V-CC for the proposed V-BB generator is a single V-T (threshold voltage), whereas that for the conventional V-BB generator is 2.V-T.
- ISSN
- 0013-5194
- Article Type
- Article
- Citation
- ELECTRONICS LETTERS, vol. 34, no. 19, page. 1831 - 1833, 1998-09-17
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Related Researcher
- 박홍준PARK, HONG JUNE
- Dept of Electrical Enginrg