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Cited 90 time in webofscience Cited 97 time in scopus
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dc.contributor.authorDAS, CR-
dc.contributor.authorKIM, J-
dc.date.accessioned2016-03-31T14:37:12Z-
dc.date.available2016-03-31T14:37:12Z-
dc.date.created2009-02-28-
dc.date.issued1994-07-
dc.identifier.issn0018-9340-
dc.identifier.other1994-OAK-0000008927-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/21940-
dc.description.abstractWe present an analytical model for the performance evaluation of hypercube computers. This analysis is aimed at modeling a deadlock-free wormhole routing scheme prevalent on second generation hypercube systems. Probability of blocking and average message delay are the two performance measures discussed here. We start with the communication traffic to find the probability of blocking. The traffic analysis can capture any message destination distribution. Next, we find the average message delay that consists of two parts. The first part is the actual message transfer delay between any source and destination nodes. The second part of the delay is due to blocking caused by the wormhole routing scheme. The analysis is also extended to virtual cut-through routing and random wormhole routing techniques. The validity of the model is demonstrated by comparing analytical results with those from simulation.-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.relation.isPartOfIEEE TRANSACTIONS ON COMPUTERS-
dc.titleHYPERCUBE COMMUNICATION DELAY WITH WORMHOLE ROUTING-
dc.typeArticle-
dc.contributor.college컴퓨터공학과-
dc.identifier.doi10.1109/12.293259-
dc.author.googleDAS, CR-
dc.author.googleKIM, J-
dc.relation.volume43-
dc.relation.startpage806-
dc.relation.lastpage814-
dc.contributor.id10074421-
dc.relation.journalIEEE TRANSACTIONS ON COMPUTERS-
dc.relation.indexSCI급, SCOPUS 등재논문-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMPUTERS, v.43, no.7, pp.806 - 814-
dc.identifier.wosidA1994NW45800004-
dc.citation.endPage814-
dc.citation.number7-
dc.citation.startPage806-
dc.citation.titleIEEE TRANSACTIONS ON COMPUTERS-
dc.citation.volume43-
dc.contributor.affiliatedAuthorKIM, J-
dc.identifier.scopusid2-s2.0-0028467067-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc53-
dc.type.docTypeArticle-
dc.subject.keywordAuthorANALYTICAL MODEL-
dc.subject.keywordAuthorBLOCKING PROBABILITY-
dc.subject.keywordAuthorDEADLOCK-
dc.subject.keywordAuthorLR ROUTING MESSAGE DELAY-
dc.subject.keywordAuthorRANDOM ROUTING-
dc.subject.keywordAuthorVIRTUAL CUT-THROUGH-
dc.subject.keywordAuthorWORMHOLE ROUTING-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-

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김종KIM, JONG
Dept of Computer Science & Enginrg
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