DC Field | Value | Language |
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dc.contributor.author | PARK, CI | - |
dc.contributor.author | PARK, YB | - |
dc.date.accessioned | 2016-03-31T14:41:56Z | - |
dc.date.available | 2016-03-31T14:41:56Z | - |
dc.date.created | 2009-02-28 | - |
dc.date.issued | 1993-11 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.other | 1993-OAK-0000008819 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/22021 | - |
dc.description.abstract | This paper presents an efficient algorithm for network partitioning problem, which improves Fiduccia and Mattheyses' (F-M's) algorithm [1]. We have noticed that the main problem of F-M's algorithm is that the cell move operation is largely influenced by the balancing constraint. In order to handle this kind of inherent limitation in F-M's algorithm, a cost function similar to the penalty function used in [121 is adopted which reflects balance degree of a partition as well as its cutset size. The weighting factor R is introduced in the cost function to determine the relative importances of the two factors: cutset size and balance degree. Using this cost function, we propose an iterative improvement algorithm which has the time complexity of O (b (m + c2)), where b is the number of blocks, m is the size of network, and c is the number of cells. It is proven that the proposed algorithm guarantees to find a balanced partition if the value of R satisfies a certain condition. Experimental results show that the proposed algorithm outperforms F-M's algorithm in most cases. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.title | AN EFFICIENT ALGORITHM FOR VLSI NETWORK PARTITIONING PROBLEM USING A COST FUNCTION WITH BALANCING FACTOR | - |
dc.type | Article | - |
dc.contributor.college | 컴퓨터공학과 | - |
dc.identifier.doi | 10.1109/43.248079 | - |
dc.author.google | PARK, CI | - |
dc.author.google | PARK, YB | - |
dc.relation.volume | 12 | - |
dc.relation.startpage | 1686 | - |
dc.relation.lastpage | 1694 | - |
dc.contributor.id | 10054851 | - |
dc.relation.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.12, no.11, pp.1686 - 1694 | - |
dc.identifier.wosid | A1993ML08900007 | - |
dc.citation.endPage | 1694 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 1686 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 12 | - |
dc.contributor.affiliatedAuthor | PARK, CI | - |
dc.identifier.scopusid | 2-s2.0-0027698031 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 4 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | BALANCE | - |
dc.subject.keywordAuthor | COST FUNCTION | - |
dc.subject.keywordAuthor | ITERATIVE IMPROVEMENT | - |
dc.subject.keywordAuthor | NETWORK | - |
dc.subject.keywordAuthor | NP-HARD | - |
dc.subject.keywordAuthor | PARTITIONING | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Interdisciplinary Applications | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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