DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, YC | - |
dc.contributor.author | Bae, JH | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2016-04-01T01:48:51Z | - |
dc.date.available | 2016-04-01T01:48:51Z | - |
dc.date.created | 2009-02-28 | - |
dc.date.issued | 2006-10 | - |
dc.identifier.issn | 1057-7130 | - |
dc.identifier.other | 2006-OAK-0000006317 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/23760 | - |
dc.description.abstract | A digital pulsewidth control loop (PWCL) with a fixed-delay rising edge and digital stability control is proposed for multiphase clock applications. In the duty-cycle tracking mode, the linear range of the input duty cycle was measured to be 28%-70%, with a maximum linearity deviation of 0.5%. In the duty-cycle correction mode, the correction range of the input duty cycle was measured to be 25%-75%, with the output duty cycle within 50 +/- 0.4%. The chip was fabricated by using a 0.25-mu m CMOS process with a 2.5-V supply. The chip area and the power consumption were 200 mu m x 250 mu m and 18 mW at an input clock frequency of 1.0 GHz, respectively. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGI | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.subject | digital PWCL | - |
dc.subject | fixed-delay rising edge | - |
dc.subject | pulsewidth control loop (PWCL) | - |
dc.subject | stability | - |
dc.subject | PULSEWIDTH CONTROL LOOP | - |
dc.title | A digital CMOS PWCL with fixed-delay rising edge and digital stability control | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1109/TCSII.2006.882186 | - |
dc.author.google | Jang, YC | - |
dc.author.google | Bae, JH | - |
dc.author.google | Park, HJ | - |
dc.relation.volume | 53 | - |
dc.relation.issue | 10 | - |
dc.relation.startpage | 1063 | - |
dc.relation.lastpage | 1067 | - |
dc.contributor.id | 10071836 | - |
dc.relation.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.53, no.10, pp.1063 - 1067 | - |
dc.identifier.wosid | 000241438800015 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 1067 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1063 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 53 | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-33750592255 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 6 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | digital PWCL | - |
dc.subject.keywordAuthor | fixed-delay rising edge | - |
dc.subject.keywordAuthor | pulsewidth control loop (PWCL) | - |
dc.subject.keywordAuthor | stability | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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