DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, TS | - |
dc.contributor.author | Ha, MH | - |
dc.contributor.author | Yoo, KD | - |
dc.contributor.author | Kang, BK | - |
dc.date.accessioned | 2016-04-01T01:58:18Z | - |
dc.date.available | 2016-04-01T01:58:18Z | - |
dc.date.created | 2009-02-28 | - |
dc.date.issued | 2006-03 | - |
dc.identifier.issn | 0167-9317 | - |
dc.identifier.other | 2006-OAK-0000005800 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/24121 | - |
dc.description.abstract | For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage oil bias temperature instability (BTI) was investigated. The gate oxide thickness, t(ox), of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V-th and of linear drain current I-JIin were measured after applying a BTI stress at a temperature of 125 degrees C. The measured shifts of V-th and I-dIin indicate that BTI oil ultra-thin gate CMOS devices appears only in the form of SiO2/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET. (c) 2005 Elsevier B.V. All rights reserved. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | ELSEVIER SCIENCE BV | - |
dc.relation.isPartOf | MICROELECTRONIC ENGINEERING | - |
dc.subject | gate oxide integrity | - |
dc.subject | bias temperature instability | - |
dc.subject | plasma process-induced damage | - |
dc.subject | interface state degradation | - |
dc.subject | latent plasma process-induced damage | - |
dc.title | Effect of plasma process-induced damage on bias temperature instability of MOSFETs | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1016/j.mee.2005.11.004 | - |
dc.author.google | Jang, TS | - |
dc.author.google | Ha, MH | - |
dc.author.google | Yoo, KD | - |
dc.author.google | Kang, BK | - |
dc.relation.volume | 83 | - |
dc.relation.issue | 3 | - |
dc.relation.startpage | 415 | - |
dc.relation.lastpage | 422 | - |
dc.contributor.id | 10071834 | - |
dc.relation.journal | MICROELECTRONIC ENGINEERING | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | MICROELECTRONIC ENGINEERING, v.83, no.3, pp.415 - 422 | - |
dc.identifier.wosid | 000236318700005 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 422 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 415 | - |
dc.citation.title | MICROELECTRONIC ENGINEERING | - |
dc.citation.volume | 83 | - |
dc.contributor.affiliatedAuthor | Kang, BK | - |
dc.identifier.scopusid | 2-s2.0-33244485283 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 2 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | gate oxide integrity | - |
dc.subject.keywordAuthor | bias temperature instability | - |
dc.subject.keywordAuthor | plasma process-induced damage | - |
dc.subject.keywordAuthor | interface state degradation | - |
dc.subject.keywordAuthor | latent plasma process-induced damage | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Optics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Optics | - |
dc.relation.journalResearchArea | Physics | - |
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