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An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation SCIE SCOPUS

Title
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation
Authors
Kim, YSSuh, YPark, HJSim, JY
Date Issued
2010-12
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Abstract
This paper presents a quantitative analysis and design methodology of resistor based phase error averaging scheme for precise multiphase generation Unlike the previously reported works stating that more averaging simply achieves better linearity the proposed analysis leads to the existence of the optimum number of averaging contributions by in eluding the effect of the signal transition time The developed model shows a good agreement with a Monte Carlo circuit simulation A test PLL with a 32 phase two dimensional wig VCO implemented in a 0 18 mu m CMOS generates monotonous 32 phases with the best linearity performance show mg an INL of +027/-1 0 LSB and a DNL of +0 37/-0 27 LSB at 1 2 GHz and an INL of +0 23/-1 57 LSB and a DNL of +044/-044 LSB at I 6 GHz
URI
https://oasis.postech.ac.kr/handle/2014.oak/25151
DOI
10.1587/TRANSELE.E93.C.1662
ISSN
0916-8524
Article Type
Article
Citation
IEICE TRANSACTIONS ON ELECTRONICS, vol. E93C, no. 12, page. 1662 - 1669, 2010-12
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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