A Low-Voltage High-Speed CMOS Inverter-Based Digital Differential Transmitter with Impedance Matching Control and Mismatch Calibration

Abstract

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a 0.18 mu m CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a 0.18 gm CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4 Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.