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Comparison of circuit reduction techniques for power network noise analysis SCIE SCOPUS KCI

Title
Comparison of circuit reduction techniques for power network noise analysis
Authors
Kim, JKim, YH
Date Issued
2009-12
Publisher
Journal of Semiconductor Technology and Science
Abstract
The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.
Keywords
Power network noise; model order reduction (MOR); PRIMA; R2Power
URI
https://oasis.postech.ac.kr/handle/2014.oak/25983
DOI
10.5573/JSTS.2009.9.4.216
ISSN
1598-1657
Article Type
Article
Citation
Journal of Semiconductor Technology and Science, vol. 9, no. 4, page. 216 - 224, 2009-12
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김영환KIM, YOUNG HWAN
Dept of Electrical Enginrg
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