DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bae, SJ | - |
dc.contributor.author | Chi, HJ | - |
dc.contributor.author | Sohn, YS | - |
dc.contributor.author | Lee, JS | - |
dc.contributor.author | Sim, JY | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2016-04-01T02:59:40Z | - |
dc.date.available | 2016-04-01T02:59:40Z | - |
dc.date.created | 2011-04-18 | - |
dc.date.issued | 2009-08 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.other | 2009-OAK-0000020951 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/26103 | - |
dc.description.abstract | A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25-mu m CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 x 120 mu m(2) and 10 mW, respectively, at the data rate of 2 Gb/s. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.subject | Decision-feedback equalization (DFE) | - |
dc.subject | DRAM interface | - |
dc.subject | equalizer | - |
dc.subject | integration | - |
dc.subject | intersymbol interference (ISI) | - |
dc.subject | multidrop bus | - |
dc.subject | single-ended signaling | - |
dc.subject | stubless channel | - |
dc.subject | DECISION-FEEDBACK EQUALIZER | - |
dc.subject | LOW-POWER | - |
dc.subject | SERIAL LINK | - |
dc.subject | DDR3 SDRAM | - |
dc.subject | INTERFACE | - |
dc.subject | DRAM | - |
dc.subject | TRANSCEIVER | - |
dc.subject | BACKPLANE | - |
dc.subject | SCHEME | - |
dc.subject | BUS | - |
dc.title | A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling | - |
dc.type | Article | - |
dc.contributor.college | 정보전자융합공학부 | - |
dc.identifier.doi | 10.1109/TCSI.2008.2010099 | - |
dc.author.google | Bae, SJ | - |
dc.author.google | Chi, HJ | - |
dc.author.google | Sohn, YS | - |
dc.author.google | Lee, JS | - |
dc.author.google | Sim, JY | - |
dc.author.google | Park, HJ | - |
dc.relation.volume | 56 | - |
dc.relation.issue | 8 | - |
dc.relation.startpage | 1645 | - |
dc.relation.lastpage | 1656 | - |
dc.contributor.id | 10071836 | - |
dc.relation.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.56, no.8, pp.1645 - 1656 | - |
dc.identifier.wosid | 000269213400003 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 1656 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1645 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 56 | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.identifier.scopusid | 2-s2.0-69449108028 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 12 | - |
dc.description.scptc | 11 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DECISION-FEEDBACK EQUALIZER | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | SERIAL LINK | - |
dc.subject.keywordPlus | DDR3 SDRAM | - |
dc.subject.keywordPlus | DRAM | - |
dc.subject.keywordPlus | TRANSCEIVER | - |
dc.subject.keywordPlus | INTERFACE | - |
dc.subject.keywordPlus | BACKPLANE | - |
dc.subject.keywordAuthor | Decision-feedback equalization (DFE) | - |
dc.subject.keywordAuthor | DRAM interface | - |
dc.subject.keywordAuthor | equalizer | - |
dc.subject.keywordAuthor | integration | - |
dc.subject.keywordAuthor | intersymbol interference (ISI) | - |
dc.subject.keywordAuthor | multidrop bus | - |
dc.subject.keywordAuthor | single-ended signaling | - |
dc.subject.keywordAuthor | stubless channel | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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