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Cited 11 time in webofscience Cited 11 time in scopus
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dc.contributor.authorKoo, Y-
dc.contributor.authorAmbrogio, S-
dc.contributor.authorWoo, J-
dc.contributor.authorSong, J-
dc.contributor.authorIelmini, D-
dc.contributor.authorHwang, H-
dc.date.accessioned2016-04-01T07:42:59Z-
dc.date.available2016-04-01T07:42:59Z-
dc.date.created2015-06-22-
dc.date.issued2015-03-
dc.identifier.issn0741-3106-
dc.identifier.other2015-OAK-0000033314-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/26793-
dc.description.abstractRetention of the low resistance state (LRS) in resistive random access memory (ReRAM) significantly decreases at increasing electrical stress due to barrier lowering of ion migration and Joule heating. The LRS failure rate under externally applied bias could be modeled by adopting an Arrhenius equation for ion migration. Accelerated retention failure under voltage stress is explained by the combination of two effects: 1) lowering of the ion migration barrier by external electric field and 2) thermal energy enhancement through local Joule heating. Based on this model, an improved methodology for ReRAM data retention test is proposed, allowing to reduce the testing temperature and the experimental time by several orders of magnitude by applying a relatively low voltage.-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.titleAccelerated Retention Test Method by Controlling Ion Migration Barrier of Resistive Random Access Memory-
dc.typeArticle-
dc.contributor.college신소재공학과-
dc.identifier.doi10.1109/LED.2015.2394302-
dc.author.googleKoo, Y-
dc.author.googleAmbrogio, S-
dc.author.googleWoo, J-
dc.author.googleSong, J-
dc.author.googleIelmini, D-
dc.author.googleHwang, H-
dc.relation.volume36-
dc.relation.issue3-
dc.relation.startpage238-
dc.relation.lastpage240-
dc.contributor.id10079928-
dc.relation.journalIEEE ELECTRON DEVICE LETTERS-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.36, no.3, pp.238 - 240-
dc.identifier.wosid000350336100008-
dc.date.tcdate2019-02-01-
dc.citation.endPage240-
dc.citation.number3-
dc.citation.startPage238-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume36-
dc.contributor.affiliatedAuthorHwang, H-
dc.identifier.scopusid2-s2.0-84924369972-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc7-
dc.description.scptc4*
dc.date.scptcdate2018-05-121*
dc.type.docTypeArticle-
dc.subject.keywordAuthorReRAM-
dc.subject.keywordAuthormemories-
dc.subject.keywordAuthorretention-
dc.subject.keywordAuthormemory fault diagnosis-
dc.subject.keywordAuthormemory testing-
dc.subject.keywordAuthoraccelerated test-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-

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