DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Y | - |
dc.contributor.author | YOO, SUNGJOO | - |
dc.contributor.author | Lee, S | - |
dc.contributor.author | Ahn, JH | - |
dc.contributor.author | Lee, K | - |
dc.date.accessioned | 2016-04-01T08:12:20Z | - |
dc.date.available | 2016-04-01T08:12:20Z | - |
dc.date.created | 2013-03-06 | - |
dc.date.issued | 2013-06 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.other | 2013-OAK-0000026693 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/27462 | - |
dc.description.abstract | Large SRAMs are the practical bottleneck to achieve a low supply voltage, because they suffer from process variation-induced bit errors at a low supply voltage. In this paper, we present an error-resilient cache architecture that resolves the drawback of previous approaches, i.e., the performance degradation at a low supply voltage which is caused by cache misses in accesses to faulty resources. We utilize cache access locality and error-free resources in a cost-effective manner. First, we classify cache lines into fully and partially accessed groups and apply appropriate methods to each group. For the partially accessed group, we propose a method of matching memory access behavior and error locations with intra-cache line word-level remapping. In order to reduce the area overhead used to store the cache access information history, we present an access pattern-learning line-fill buffer (LFB). For the fully accessed group, we propose the utilization of error-free assist functions in the cache, i.e., a LFB and victim cache with no process variation-induced error at the target minimum supply voltage. We also present an error-aware prefetch method that allows us to utilize the error-free victim cache to achieve a further reduction in cache misses due to faulty resources. Experimental results show that the proposed method gives an average 32.6% reduction in cycles per instruction at an error rate of 0.2% with a small area overhead of 8.2%. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.title | MAEPER: Matching Access and Error Patterns with Error-free Resource for Low Vcc L1 Cache | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1109/TVLSI.2012.2202931 | - |
dc.author.google | Choi Y., Yoo S., Lee S., Ahn J.H., Lee K. | - |
dc.relation.volume | 21 | - |
dc.relation.issue | 6 | - |
dc.relation.startpage | 1013 | - |
dc.relation.lastpage | 1026 | - |
dc.contributor.id | 10077436 | - |
dc.relation.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.6, pp.1013 - 1026 | - |
dc.identifier.wosid | 000319473000003 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 1026 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1013 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 21 | - |
dc.contributor.affiliatedAuthor | YOO, SUNGJOO | - |
dc.contributor.affiliatedAuthor | Lee, S | - |
dc.identifier.scopusid | 2-s2.0-84878268997 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 2 | - |
dc.description.scptc | 4 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Bit error | - |
dc.subject.keywordAuthor | cache architecture | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | persistent error | - |
dc.subject.keywordAuthor | process variation | - |
dc.subject.keywordAuthor | SRAM | - |
dc.subject.keywordAuthor | Vccmin | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
library@postech.ac.kr Tel: 054-279-2548
Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.