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Method of extracting effective channel length for nano-scale n-MOSFETs SCIE SCOPUS

Title
Method of extracting effective channel length for nano-scale n-MOSFETs
Authors
Choi, HWLee, NHKang, HSKang, BK
Date Issued
2009-10
Publisher
PERGAMON-ELSEVIER SCIENCE LTD
Abstract
This paper proposes a method of extracting the effective channel length L-eff of nano-scale n-MOSFETs. This method requires only one MOSFET; therefore, the L-eff extraction is not affected either by variation of carrier mobility due to differences in gate length or by changes in MOSFET parameters due to differences in fabrication processes. The method is based on the facts that the gate tunneling current I-gb to the substrate depends on L-eff, and that the gate tunneling current I-gsd to the source and drain depends on the gate-source/drain overlap length Delta L. Curves of I-gb and I-gsd versus the gate dielectric voltage V-ox were obtained from the measured curves of I-gb and I-gsd versus gate voltage V-g in n-MOSFETs fabricated using a 90 nm CMOS technology. L-eff was extracted from the ratio I-gb/I-gsd for a given V-ox, Comparison of the drain current I-d versus V-d curves calculated using the extracted L(eff)s with the same curves obtained using previous methods shows that the proposed method is much more accurate than the previous ones. (C) 2009 Elsevier Ltd. All rights reserved.
Keywords
MOSFET; Effective channel length; Nano-scale MOSFET; Gate leakage current; Gate tunneling current; SERIES RESISTANCE; SHIFT; OXIDE
URI
https://oasis.postech.ac.kr/handle/2014.oak/27611
DOI
10.1016/J.SSE.2009.06.014
ISSN
0038-1101
Article Type
Article
Citation
SOLID-STATE ELECTRONICS, vol. 53, no. 10, page. 1076 - 1085, 2009-10
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강봉구KANG, BONG KOO
Dept of Electrical Enginrg
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