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dc.contributor.authorLee, NH-
dc.contributor.authorChoi, HW-
dc.contributor.authorKang, H-
dc.contributor.authorKang, B-
dc.date.accessioned2016-04-01T08:16:41Z-
dc.date.available2016-04-01T08:16:41Z-
dc.date.created2010-01-19-
dc.date.issued2009-11-
dc.identifier.issn0741-3106-
dc.identifier.other2009-OAK-0000019798-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/27615-
dc.description.abstractAn experimental method of extracting the effective channel length L-eff from measured gate tunneling current (I-g) of nanoscale n-MOSFETs is proposed. The tunneling current from gate to the source and drain (I-gsd) was measured while applying a reverse bias to the substrate, and it was corrected for the depletion effect of the source/drain junctions. The gate tunneling current to the substrate (I-gc) was obtained by subtracting I-gsd from I-g. L-eff was calculated using a linear extrapolation of the I-gc versus gate length plot. The proposed method is a very simple and quite accurate method of extracting L-eff which does not require any additional assumptions and parameter extraction.-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGI-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.subjectEffective channel length-
dc.subjectgate-source/drain overlap length-
dc.subjectgate tunneling current-
dc.subjectMOSFET-
dc.subjectSHIFT-
dc.titleExperimental Method to Extract Effective Channel Length of Nanoscale n-MOSFETs-
dc.typeArticle-
dc.contributor.college전자전기공학과-
dc.identifier.doi10.1109/LED.2009.203-
dc.author.googleLee, NH-
dc.author.googleChoi, HW-
dc.author.googleKang, H-
dc.author.googleKang, B-
dc.relation.volume30-
dc.relation.issue11-
dc.relation.startpage1191-
dc.relation.lastpage1193-
dc.contributor.id10071834-
dc.relation.journalIEEE ELECTRON DEVICE LETTERS-
dc.relation.indexSCI급, SCOPUS 등재논문-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.30, no.11, pp.1191 - 1193-
dc.identifier.wosid000271151500025-
dc.date.tcdate2018-03-23-
dc.citation.endPage1193-
dc.citation.number11-
dc.citation.startPage1191-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume30-
dc.contributor.affiliatedAuthorKang, B-
dc.description.journalClass1-
dc.description.journalClass1-
dc.type.docTypeArticle-
dc.subject.keywordAuthorEffective channel length-
dc.subject.keywordAuthorgate-source/drain overlap length-
dc.subject.keywordAuthorgate tunneling current-
dc.subject.keywordAuthorMOSFET-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-

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강봉구KANG, BONG KOO
Dept of Electrical Enginrg
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