A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

Abstract

A current-mode bidirectional I/O buffer was designed, and the maximum effective bandwidth of 1.0 Gb/s per wire was obtained from measurements. To enhance the operating speed, the voltage swing on the transmission line was reduced to 0.5 V and the internal nodes of the buffer were designed to be low impedance nodes using the current-mode scheme. An automatic impedance-matching scheme was used to generate bias voltages, which adjust output resistance of the buffer to be equal to the characteristic impedance of the transmission line in spite of process variations. The chip was fabricated by using a 0.8-mu m CMOS technology. The chip size was 500 x 330 mu m(2), and the power consumption was 50 mW at a supply voltage of 3 V.