A low-voltage OP amp with digitally controlled algorithmic approximation

Abstract

This paper presents a new architecture of digitally controlled algorithmic OP amp suitable for scaled CMOS technologies. With inverter-based gain stages and digitally-assisted damping control, the amplifier achieves high-gain and wide input/output ranges even at the minimally allowable supply voltage by digital circuits. The amplifier, implemented in a standard 0.18 mu m CMOS, shows a DC gain of 73 dB and 95 % settling time of 41 ns at 0.5 V step input.