A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs
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SCOPUS
- Title
- A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs
- Authors
- Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Sim, JY; Park, HJ
- Date Issued
- 2016-02
- Publisher
- IEEE
- Abstract
- A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm(2).
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/35984
- DOI
- 10.1109/TCSII.2015.2468911
- ISSN
- 1549-7747
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, vol. 63, no. 2, page. 141 - 145, 2016-02
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