DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kwon, HJ | - |
dc.contributor.author | Lim, JH | - |
dc.contributor.author | Kim, B | - |
dc.contributor.author | Sim, JY | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2017-07-19T12:41:49Z | - |
dc.date.available | 2017-07-19T12:41:49Z | - |
dc.date.created | 2016-01-21 | - |
dc.date.issued | 2015-06 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/36281 | - |
dc.description.abstract | Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s similar to 8 Gb/s at 1.2 V, 4 Gb/s similar to 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s. | - |
dc.language | English | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.title | An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors | - |
dc.type | Article | - |
dc.identifier.doi | 10.5573/JSTS.2015.15.3.404 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.15, no.3, pp.404 - 416 | - |
dc.identifier.wosid | 000366060900012 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 416 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 404 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 15 | - |
dc.contributor.affiliatedAuthor | Kim, B | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-84936776843 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 3 | - |
dc.description.scptc | 3 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | CLOCK | - |
dc.subject.keywordPlus | ACQUISITION | - |
dc.subject.keywordPlus | TRANSCEIVER | - |
dc.subject.keywordAuthor | Clock and data recovery circuit | - |
dc.subject.keywordAuthor | fine frequency detection | - |
dc.subject.keywordAuthor | jitter tolerance | - |
dc.subject.keywordAuthor | referenceless | - |
dc.subject.keywordAuthor | adaptive bandwidth | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
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