Solution-Processed Vertically Stacked Complementary Organic Circuits with Inkjet-Printed Routing

Abstract

The fabrication and measurements of solution‐processed vertically stacked complementary organic field‐effect transistors (FETs) with a high static noise margin (SNM) are reported. In the device structure, a bottom‐gate p‐type organic FET (PFET) is vertically integrated on a top‐gate n‐type organic FET (NFET) with the gate shared in‐between. A new strategy has been proposed to maximize the SNM by matching the driving strengths of the PFET and the NFET by independently adjusting the dielectric capacitance of each type of transistor. Using ideally balanced inverters with the transistor‐on‐transistor structure, the first examples of universal logic gates by inkjet‐printed routing are demonstrated. It is believed that this work can be extended to large‐scale complementary integrated circuits with a high transistor density, simpler routing path, and high yield.