DC Field | Value | Language |
---|---|---|
dc.contributor.author | Soo-Min Lee | - |
dc.contributor.author | Ji-Hoon Lim | - |
dc.contributor.author | Il-Min Yi | - |
dc.contributor.author | Young-Jae Jang | - |
dc.contributor.author | Jung, HK | - |
dc.contributor.author | Kyunghoon Kim | - |
dc.contributor.author | Daehan Kwon | - |
dc.contributor.author | Kim, B | - |
dc.contributor.author | Sim, JY | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2017-07-19T13:31:00Z | - |
dc.date.available | 2017-07-19T13:31:00Z | - |
dc.date.created | 2017-02-13 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37137 | - |
dc.description.abstract | A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of similar to 10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE Journal of Solid-State Circuits | - |
dc.title | A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2016.2559512 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE Journal of Solid-State Circuits, v.51, no.8, pp.1890 - 1901 | - |
dc.identifier.wosid | 000382169400014 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 1901 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1890 | - |
dc.citation.title | IEEE Journal of Solid-State Circuits | - |
dc.citation.volume | 51 | - |
dc.contributor.affiliatedAuthor | Kim, B | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-84971382105 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 2 | - |
dc.description.scptc | 2 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Balanced coding | - |
dc.subject.keywordAuthor | DRAM interface | - |
dc.subject.keywordAuthor | electromagnetic interference (EMI) | - |
dc.subject.keywordAuthor | H-field measurement | - |
dc.subject.keywordAuthor | parallel links | - |
dc.subject.keywordAuthor | single-ended | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordAuthor | 4-bit 4-wire 4-level signaling | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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