DC Field | Value | Language |
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dc.contributor.author | Lee, K | - |
dc.contributor.author | Sim, JY | - |
dc.date.accessioned | 2017-07-19T13:31:12Z | - |
dc.date.available | 2017-07-19T13:31:12Z | - |
dc.date.created | 2017-02-13 | - |
dc.date.issued | 2016-04 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37144 | - |
dc.description.abstract | This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking techniques to reduce design complexity for the half-rate data recovery. In the proposed receiver, the use of wideband injection-locked oscillator (ILO) greatly suppresses its phase noise while the narrowband digital phase tracking loop (DPTL) tunes retiming phase. For wide-range and continuous-rate operation, four circuit techniques have been adopted: a VCO with active inductance load for low VCO gain at high frequency, a wide-range digitally-controlled delay line (DCDL) with adaptive band selection, a linearized delay control unit with CM-to-delay conversion technique, and a coarse frequency detection scheme to drive the free-running oscillator frequency toward injection locking. The prototype CDR, fabricated in low power CMOS 65 nm technology, successfully detects 0.8-6.5 Gb/s data rates over 5 '' FR4 trace with 2(31) - 1 PRBS pattern satisfying BER < 10-12. The power efficiency was 2.4 mW/Gb/s at 6.5 Gb/s. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.title | A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TCSI.2016.2528480 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.4, pp.482 - 493 | - |
dc.identifier.wosid | 000375276300004 | - |
dc.date.tcdate | 2018-03-23 | - |
dc.citation.endPage | 493 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 482 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 63 | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.identifier.scopusid | 2-s2.0-84977962755 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.scptc | 0 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | PHASE | - |
dc.subject.keywordPlus | ACQUISITION | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordAuthor | Clock and data recovery | - |
dc.subject.keywordAuthor | common-mode clock-embedded signaling | - |
dc.subject.keywordAuthor | high-speed I/O | - |
dc.subject.keywordAuthor | injection-locked oscillator | - |
dc.subject.keywordAuthor | reference-less CDR | - |
dc.subject.keywordAuthor | wireline transceivers | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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