Efficient parallel architecture for linear feedback shift registers

Abstract

This brief presents a new parallel architecture for linear feedback shift registers (LFSRs), which can be used to achieve high-throughput Bose-Chaudhuri-Hocquenghemor cyclic redundancy check encoders for storage and communication systems. While previous parallel LFSR architectures have computed values by using the past input messages and the register outputs, the proposed parallel architecture based on the transposed serial LFSR calculates the output by using only the past feedback values. As a result, the proposed architecture reduces the area-time product by up to 59% compared with the recent architecture.