Area-efficient method to approximate two minima for LDPC decoders

Abstract

A simple yet effective method is proposed to reduce the hardware complexity of min-sum-based low-density parity-check (LDPC) decoders. The proposed method finds the second minimum from the last four candidates of the first minimum, and can be implemented with only a few hardware components. In the case of 64 inputs, the proposed method reduces the comparators and 2-to-1 multiplexers by 48 and 64% compared to the conventional method that finds two exact minima.