DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, JW | - |
dc.contributor.author | Attarimashalkoubeh, B | - |
dc.contributor.author | Prakash, A | - |
dc.contributor.author | Hwang, H | - |
dc.contributor.author | Jeong, Yoon-Ha | - |
dc.date.accessioned | 2017-07-19T13:50:11Z | - |
dc.date.available | 2017-07-19T13:50:11Z | - |
dc.date.created | 2017-02-27 | - |
dc.date.issued | 2016-06 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37697 | - |
dc.description.abstract | A novel neuron circuit using a Cu/Ti/Al2O3-based conductive-bridge random access memory (CBRAM) device for hardware neural networks that utilize nonvolatile memories as synaptic weights is introduced. The neuronal operations are designed and proved using SPICE simulations with a Verilog-A device model based on the measured characteristics of the CBRAM device. The applicability of the neuron is demonstrated by constructing a neural network system and applying it to pattern reconstructions that can recall the original patterns from noisy patterns. With these CBRAM-based neurons, a reduction in the area and power of neuromorphic chips is expected in comparison with CMOS-only neuron implementations. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.title | Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TED.2016.2549359 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.6, pp.2610 - 2613 | - |
dc.identifier.wosid | 000378592800058 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 2613 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 2610 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 63 | - |
dc.contributor.affiliatedAuthor | Hwang, H | - |
dc.contributor.affiliatedAuthor | Jeong, Yoon-Ha | - |
dc.identifier.scopusid | 2-s2.0-84979493647 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 3 | - |
dc.description.scptc | 1 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Conductive-bridge random access memory (CBRAM) | - |
dc.subject.keywordAuthor | hardware neural network | - |
dc.subject.keywordAuthor | integrate-and-fire neuron | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
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