DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, JS | - |
dc.contributor.author | Jeong, EY | - |
dc.contributor.author | Baek, CK | - |
dc.contributor.author | Kim, YR | - |
dc.contributor.author | Hong, JH | - |
dc.contributor.author | Lee, JS | - |
dc.contributor.author | Baek, RH | - |
dc.contributor.author | Jeong, YH | - |
dc.date.accessioned | 2017-07-19T13:51:54Z | - |
dc.date.available | 2017-07-19T13:51:54Z | - |
dc.date.created | 2017-02-22 | - |
dc.date.issued | 2015-10 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37757 | - |
dc.description.abstract | DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.title | Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LED.2015.2464706 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.36, no.10, pp.994 - 996 | - |
dc.identifier.wosid | 000362288700002 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 996 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 994 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 36 | - |
dc.contributor.affiliatedAuthor | Baek, CK | - |
dc.contributor.affiliatedAuthor | Lee, JS | - |
dc.contributor.affiliatedAuthor | Baek, RH | - |
dc.contributor.affiliatedAuthor | Jeong, YH | - |
dc.identifier.scopusid | 2-s2.0-84957037778 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 7 | - |
dc.description.scptc | 6 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | LEAKAGE | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordAuthor | Si | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | parasitic capacitances | - |
dc.subject.keywordAuthor | RC delay | - |
dc.subject.keywordAuthor | underlap | - |
dc.subject.keywordAuthor | 7-nm node | - |
dc.subject.keywordAuthor | SOC | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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