Impact of Spacer Dielectric Constant on Parasitic RC and Design Guidelines to Optimize DC/AC Performance in 10 nm Node Si-Nanowire FETs

Abstract

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (kappa(sp)), extension length (L-EXT), nanowire diameter (D-nw), and operation voltage (V-DD) for the sub-10nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (R-SD) and capacitances (C-para). Compared with low-kappa spacers, high-kappa spacers exhibit a higher on/off-current ratio with a lower R-SD, but show severe degradation in their AC performance owing to a higher C-para. Considering the trade-off between R-SD and C-para, optimal geometry-dependent kappa(sp) values at various supply voltages (V-DD) are determined using gate delay (CV/I) and current-gain cutoff frequency (t(T)). We found that as L-EXT and V-DD decrease and D-nw increases, the optimal kappa(sp) value shifts from the high-kappa to low-kappa regime. (C) 2015 The Japan Society of Applied Physics