A 2-8 GHz adaptive duty-cycle corrector loop with background calibration

Abstract

A novel adaptive duty-cycle correction (DCC) architecture based on background calibration is developed. The proposed DCC loop is capable of correcting 17-80% duty error up to 4.6% at 8.1GHz within 172ns convergent time. During calibration, the whole loop including DCC buffer consumes 6.4mA from 0.95V supply but after calibration, digital feedback section does not burn additional dynamic power. The corner results show that the proposed calibration methodology can cope with process, voltage and temperature (PVT) variation adaptively. The architecture is implemented in 45nm CMOS process and occupies 0.0032mm(2).