All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
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- Title
- All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
- Authors
- Seong, Kihwan; Lee, Won-Cheol; Kim, Byungsub; SIM, JAE YOON; PARK, HONG JUNE
- Date Issued
- 2016-06
- Publisher
- IEEK PUBLICATION CENTER
- Abstract
- A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies 0.038 mm(2), consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/39258
- DOI
- 10.5573/JSTS.2016.16.3.352
- ISSN
- 1598-1657
- Article Type
- Article
- Citation
- Journal of Semiconductor Technology and Science, vol. 16, no. 3, page. 352 - 358, 2016-06
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