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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | S. Lee | - |
| dc.contributor.author | K. G. Shin | - |
| dc.date.accessioned | 2018-01-08T11:13:54Z | - |
| dc.date.available | 2018-01-08T11:13:54Z | - |
| dc.date.created | 2009-03-26 | - |
| dc.date.issued | 1990-01 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/40108 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
| dc.title | DESIGN-FOR-TEST USING PARTIAL PARALLEL SCAN | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.9, no.2, pp.203 - 211 | - |
| dc.citation.endPage | 211 | - |
| dc.citation.number | 2 | - |
| dc.citation.startPage | 203 | - |
| dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
| dc.citation.volume | 9 | - |
| dc.contributor.affiliatedAuthor | S. Lee | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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- 이승구LEE, SUNG GU
- Dept of Electrical Enginrg