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Cited 3 time in webofscience Cited 7 time in scopus
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dc.contributor.authorKim, Jungsik-
dc.contributor.authorOh, Hyeongwan-
dc.contributor.authorKim, Jiwon-
dc.contributor.authorMeyyappan, M.-
dc.contributor.authorLee, Jeong-Soo-
dc.date.accessioned2018-05-04T02:41:26Z-
dc.date.available2018-05-04T02:41:26Z-
dc.date.created2018-03-02-
dc.date.issued2017-01-
dc.identifier.issn0021-4922-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/41286-
dc.description.abstractEffects of using asymmetric channel thickness in tunneling field-effect transistors (TFET) are investigated in sub-50 nm channel regime using two-dimensional (2D) simulations. As the thickness of the source side becomes narrower in narrow-source wide-drain (NSWD) TFETs, the threshold voltage (V th) and the subthreshold swing (SS) decrease due to enhanced gate controllability of the source side. The narrow source thickness can make the band-to-band tunneling (BTBT) distance shorter and induce much higher electric field near the source junction at the on-state condition. In contrast, in a TFET with wide-source narrow-drain (WSND), the SS shows almost constant values and the V th slightly increases with narrowing thickness of the drain side. In addition, the ambipolar current can rapidly become larger with smaller thickness on the drain side because of the shorter BTBT distance and the higher electric-field at the drain junction. The on-current of the asymmetric channel TFET is lower than that of conventional TFETs due to the volume limitation of the NSWD TFET and high series resistance of the WSND TFET. The on-current is almost determined by the channel thickness of the source side.-
dc.languageEnglish-
dc.publisherJAPAN SOC APPLIED PHYSICS-
dc.relation.isPartOfJAPANESE JOURNAL OF APPLIED PHYSICS-
dc.titleElectrical characteristics of tunneling field-effect transistors with asymmetric channel thickness-
dc.typeArticle-
dc.identifier.doi10.7567/JJAP.56.024201-
dc.type.rimsART-
dc.identifier.bibliographicCitationJAPANESE JOURNAL OF APPLIED PHYSICS, v.56, no.2, pp.024201-1 - 024201-5-
dc.identifier.wosid000393960800001-
dc.date.tcdate2019-02-01-
dc.citation.endPage024201-5-
dc.citation.number2-
dc.citation.startPage024201-1-
dc.citation.titleJAPANESE JOURNAL OF APPLIED PHYSICS-
dc.citation.volume56-
dc.contributor.affiliatedAuthorKim, Jungsik-
dc.contributor.affiliatedAuthorOh, Hyeongwan-
dc.contributor.affiliatedAuthorKim, Jiwon-
dc.contributor.affiliatedAuthorLee, Jeong-Soo-
dc.identifier.scopusid2-s2.0-85011554848-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc1-
dc.type.docTypearticle-
dc.subject.keywordPlusQUANTUM CONFINEMENT-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusFET-
dc.subject.keywordPlusMOBILITY-
dc.subject.keywordPlusMOSFETS-
dc.subject.keywordPlusIMPACT-
dc.subject.keywordPlusTFETS-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaPhysics-

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이정수LEE, JEONG SOO
Dept of Electrical Enginrg
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