DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Seungnam | - |
dc.contributor.author | Ku, Hwan-Seok | - |
dc.contributor.author | Son, Hyunwoo | - |
dc.contributor.author | KIM, BYUNGSUB | - |
dc.contributor.author | PARK, HONG JUNE | - |
dc.contributor.author | SIM, JAE YOON | - |
dc.date.accessioned | 2018-05-04T02:48:19Z | - |
dc.date.available | 2018-05-04T02:48:19Z | - |
dc.date.created | 2018-02-06 | - |
dc.date.issued | 2018-02 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/41349 | - |
dc.description.abstract | This paper presents an asynchronous-clocking successive approximation register (SAR) analog-to-digital converter (ADC) suitable for ultralow-power fine-precision sensor applications whose signal bandwidth is in the kilohertz range. The performance-limiting issues of comparator noise and capacitor mismatch in SAR ADC are resolved by a residue integration scheme combined with a dynamic element matching (DEM), achieving a high resolution without imposing extra burden on the design of residue amplifier and comparator. The prototype 16-bit 2 kS/s SAR ADC is fabricated using 180-nm CMOS process in an area of 0.68 mm2. Measurements show 84.6-dB signal to noise and distortion ratio and 98.2-dB spurious-free dynamic range at the Nyquist input frequency. The ADC dissipates 7.93 μW from supply voltage of 1.8 V and achieves a Schreier figure of merit of 165.6 dB. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.subject | Approximation theory | - |
dc.subject | Comparator circuits | - |
dc.subject | Comparators (optical) | - |
dc.subject | Frequency converters | - |
dc.subject | Signal to noise ratio | - |
dc.subject | Surveying | - |
dc.subject | Analog to digital converters | - |
dc.subject | Dynamic element matching | - |
dc.subject | Low power sensor | - |
dc.subject | Nyquist rate | - |
dc.subject | Successive approximation register | - |
dc.subject | Analog to digital conversion | - |
dc.title | An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2017.2774287 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.2, pp.404 - 417 | - |
dc.identifier.wosid | 000423546800006 | - |
dc.date.tcdate | 2018-04-06 | - |
dc.citation.endPage | 417 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 404 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 53 | - |
dc.contributor.affiliatedAuthor | Ku, Hwan-Seok | - |
dc.contributor.affiliatedAuthor | Son, Hyunwoo | - |
dc.contributor.affiliatedAuthor | KIM, BYUNGSUB | - |
dc.contributor.affiliatedAuthor | PARK, HONG JUNE | - |
dc.contributor.affiliatedAuthor | SIM, JAE YOON | - |
dc.identifier.scopusid | 2-s2.0-85041296983 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 0 | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | dynamic element matching (DEM) | - |
dc.subject.keywordAuthor | low-power sensor application | - |
dc.subject.keywordAuthor | Nyquist-rate ADC | - |
dc.subject.keywordAuthor | successive approximation register (SAR) ADC | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
library@postech.ac.kr Tel: 054-279-2548
Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.