Open Access System for Information Sharing

Login Library
검색

  OASIS Repository@POSTECHLIBRARY

Browsing "2. Conference Papers" by  Title

전체 가 나 다 라 마 바 사 아 자 차 카 타 파 하
All 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:
Showing results 101 to 120 of 5,936
Conference
8 PSK 통신시스템에 사용된 trellis code의 효율적인 거리스펙트럼 계산

제3회 통신정보합동 학술대회, page. 172 - 177, 1993-04-01

Conference
8-GS/s 4-비트 CMOS 타임 인터리브 플래쉬 아날로그/디지털 변환기

한국군사과학기술학회 종합학술대회, page. 405 - 408, 2003-08-01

Conference
8088 CPU에서 모듈라 곱셈의 구현

제5회 통신정보 합동 학술대회, page. 42 - 46, 1995-04-01

Conference
840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to processor communication

Symposium on VLSI Circuits, page. 23 - 24, 1999-06-17

Conference
840 Mb/s CMOS Demultiplexed Equalizing Transceiver for DRAM-to Processor Communication

Symp.On VLSI Circuits Digest of Technical Papers, page. 23 - 24, 1999-06-01

Conference
8비트 마이크로소프트에 적합한 볼록암호 알고리즘

한국통신정보보호학회 종합학술발표회, page. 303 - 314, 1997-11-01

Conference
900 MHz대 휴대폰용 MMIC 혼합기의 설계 및 제작

마이크로파 및 전파전파 학술발표회, page. 59 - 63, 1996-05-01

Conference
A Selective Normalized Subband Adaptive Filter Exploiting an Efficient Subset of Subband

19th European Signal Processing Conference (EUSIPCO 2011), 2011-08-29

Conference
A 0.0047mm2 Highly Synthesizable TDC and DCO-less Fractional-NPLL with a Seamless Lock - Range off RER to 1GHz

IEEE International Solid-State Circuits Conference, 2017-02-07

Conference
A 0.0047mm2 Highly Synthesizable TDC and DCO-less Fractional-NPLL with a Seamless Lock - Range off RER to 1GHz

IEEE International Solid-State Circuits Conference (ISSCC), 2017-02-07

Conference
A 0.0047mm2 Highly Synthesizable TDC- and DCO-Less Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz

IEEE International Solid-State Circuits Conference, 2017-02-05

Conference
A 0.1-fref BW 1GHz Fractional-N PLL with FIR-Embedded Phase-Interpolator-Based Noise Filtering

IEEE International Solid-State Circuits Conference, page. 94 - 95, 2011-02-21

Conference
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

ISSCC 2011, 2011-02-20

Conference
A 0.12GHz-1.4GHz DLL-based clock generator with a multiplied 4-phase clock using a 0.18um CMOS process

International SoC Design Conference, page. 241 - 244, 2006-10-01

Conference
A 0.13-μm CMOS Multi-Divider for 100 MHz ~ 1 GHz Frequency Synthesizer

대한전자공학회 2010 하계종합학술대회, 2010-06-16

Conference
A 0.18-um CMOS switch with high isolation for 48 MHz ~ 860 MHz TV tuner application

대한전자공학회 2009 하계종합학술대회, 2009-07-08

Conference
A 0.3 mm 2 Miniaturized X-Band On-Chip Slot Antenna in 0.13μm CMOS

Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE, 2007-07-02

Conference
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC

IEEE International Solid-State Circuits Conference, 2018-02-13

Conference
A 0.3-to-1.2V Frequency-Scalable Fractional-N ADPLLwith a Speculative Dual-Referenced Interpolating TDC

EEE International Solid-State Circuits Conference (ISSCC), 2018-02-13

Conference
A 0.4 V Driving Multi-Touch Capacitive Sensor with the Driving Signal Frequency set to (n+0.5) Times the Inverse of the LCD VCOM Noise Period

International Symposium on Circuits and System, 2014-06-01

1 2 3 4 5 6 7 8 9 10 11 297
개인정보처리방침 Personal Information Protection Policy

library@postech.ac.kr Tel: 054-279-2548

Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.

Browse

Login Library Help