DC Field | Value | Language |
---|---|---|
dc.contributor.author | RHU, MINSOO | - |
dc.contributor.author | O'CONNOR MIKE | - |
dc.contributor.author | CHATTERJEE, NILADRISH | - |
dc.contributor.author | POOL, JEFF | - |
dc.contributor.author | KWON, YOUNGEUN | - |
dc.contributor.author | KECKLER, STEPHEN | - |
dc.date.accessioned | 2018-05-11T00:14:53Z | - |
dc.date.available | 2018-05-11T00:14:53Z | - |
dc.date.created | 2018-03-29 | - |
dc.date.issued | 2018-02-26 | - |
dc.identifier.issn | 2378-203X | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/42572 | - |
dc.description.abstract | Popular deep learning frameworks require users to fine-tune their memory usage so that the training data of a deep neural network (DNN) fits within the GPU physical memory. Prior work tries to address this restriction by virtualizing the memory usage of DNNs, enabling both CPU and GPU memory to be utilized for memory allocations. Despite its merits, virtualizing memory can incur significant performance overheads when the time needed to copy data back and forth from CPU memory is higher than the latency to perform DNN computations. We introduce a high-performance virtualization strategy based on a "compressing DMA engine" (cDMA) that drastically reduces the size of the data structures that are targeted for CPU-side allocations. The cDMA engine offers an average 2.6x (maximum 13.8x) compression ratio by exploiting the sparsity inherent in offloaded data, improving the performance of virtualized DNNs by an average 53% (maximum 79%) when evaluated on an NVIDIA Titan Xp. | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE International Symposium on High-Performance Computer Architecture | - |
dc.relation.isPartOf | Proceedings of the 24th IEEE International Symposium on High-Performance Computer Architecture | - |
dc.title | Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | IEEE International Symposium on High-Performance Computer Architecture, pp.78 - 91 | - |
dc.citation.conferenceDate | 2018-02-24 | - |
dc.citation.conferencePlace | AU | - |
dc.citation.endPage | 91 | - |
dc.citation.startPage | 78 | - |
dc.citation.title | IEEE International Symposium on High-Performance Computer Architecture | - |
dc.contributor.affiliatedAuthor | RHU, MINSOO | - |
dc.contributor.affiliatedAuthor | KWON, YOUNGEUN | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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